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st16c2552 plcc package dual asynchronous receiver/transmitter with fifos description the st16c2552 is a dual asynchronous receiver and transmitter with 16 byte transmit and receive fifos. independent programmable baud rate generators are provided to select transmit and receive clock rates from 50hz to 1.5 mhz for each uart. the on board status registers of the st16c2552 provide the error conditions, type and status of the transfer operation being performed. complete mo- dem control capability and a processor interrupt system that may be software tailored to the users requirements are included. the st16c2552 provides internal loop-back capability for on board diagnostic testing. signalling for dma transfers is done through two pins per channel ( txrdy*, rxrdy* ). the rxrdy* function is multiplexed on one pin with the op2* and baudout functions. cpu can select these functions through the alternate function register. the st16c2552 is fabricated in an advanced 0.6 m cmos process to achieve low power and high speed requirements. features pin to pin and functional compatible to national ns16c552 16 byte transmit fifo 16 byte receive fifo with error flags modem control signals (cts*, rts*, dsr*, dtr*, ri*, cd*) programmable character lengths (5, 6, 7, 8) bits even, odd, or no parity bit generation and detection status report register ttl compatible inputs, outputs independent transmit and receive control software compatible with ins8250, ns16c550 460.8 khz transmit/receive operation with 7.372 mhz crystal or external clock source ordering information part number package operating temperature st16c2552cj44 plcc 0 c to + 70 c st16c2552ij44 plcc -40 c to + 85 c printed december 17, 1996 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 d5 d6 d7 a0 xtal1 gnd xtal2 a1 a2 chsel intb cs* mfb* iow* reset gnd rtsb* ior* rxb txb dtrb* ctsb* rxa txa dtra* rtsa* mfa* inta vcc txrdyb* rib* cdb* dsrb* d4 d3 d2 d1 d0 txrdya* vcc ria* cda* dsra* ctsa* st16c2552cj44 startech an company rev. 2.0 3-135 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 st16c2552cq48 n.c. d5 d6 d7 a0 xtal1 gnd xtal2 a1 a2 ch sel intb n.c. cs* mf b* iow* reset gnd rtsb* ior* rxb txb dtr b* ctsb* rxa txa dtr a* rtsa* mf a* inta vcc txrdyb* rib* cd b* dsrb* n.c. d4 d3 d2 d1 d0 txrdya* vcc ria* cd a* dsra* ctsa* n.c.
3-136 st16c2552 st16c2552 block diagram d0-d7 ior* iow* reset a0-a2 cs* chsel inta intb txrdy* a/b rxrdy* a/b dtr a/b* rts a/b* mf a/b* cts a/b* ri a/b* cd a/b* dsr a/b* tx a/b rx a/b data bus & control logic register select logic modem control logic interrupt control logic transmit fifo registers transmit shift register receive fifo registers receive shift register inter connect bus lines & control signals clock & baud rate generator xtal1 xtal2
3-137 st16c2552 st16c2552 symbol pin signal type pin description symbol description d0-d7 2-9 i/o bi-directional data bus. eight bit, three state data bus to transfer information to or from the cpu. d0 is the least significant bit of the data bus and the first serial data bit to be received or transmitted. rx a/b 39,25 i serial data input a/b. the serial information (data) received from serial port to st16c2552 receive input circuit. a mark (high) is logic one and a space (low) is logic zero. during the local loopback mode the rx input is disabled from external connection and connected to the tx output internally. tx a/b 38,26 o serial data output a/b. the serial data is transmitted via this pin with additional start , stop and parity bits. the tx will be held in mark (high) state during reset, local loopback mode or when the transmitter is disabled. cs* 18 i chip select. (active low) a low at this pin enables the st16c2552 / cpu data transfer operation. chsel 16 i uart a/b select. uart a or b can be selected by changing the state of this pin when cs* is active. low on this pin, selects the uart b and high on this pin selects uart a section. xtal1 11 i crystal input 1 or external clock input. a crystal can be connected to this pin and xtal2 pin to utilize the internal oscillator circuit. an external clock can be used to clock internal circuit and baud rate generator for custom transmis- sion rates. xtal2 13 o crystal input 2 or buffered clock output. see xtal1. should be left open if a clcok is connected to xtal1. iow* 20 i write strobe. (active low) a low on this pin will transfer the contents of the cpu data bus to the addressed register. ior* 24 i read strobe. (active low) a low level on this pin transfers the contents of the st16c2552 data bus to the cpu. a0-a2 10,14,15 i address select lines. to select internal registers.
3-138 st16c2552 st16c2552 symbol pin signal type pin description symbol description int a/b 34,17 o interrupt output a/b. (active high) this pin goes high (when enabled by the interrupt enable register) whenever a re- ceiver error, receiver data available, transmitter empty, or modem status condition flag is detected. mf* a/b 35,19 o op2* (interrupt enable), baudout* and rxrdy* outputs. these outputs are multiplexed via alternate function reg- ister. when output enable function is selected the mf* pin stays high when int out pin is set to three state mode and goes low when int pin is enabled. see bit-3 modem control register (mcr bit-3). when baudout function is selected, the 16 x tx/rx baud rate clock output is generated. rxrdy function can be selected to use to request a dma transfer of data from the receive data fifo. op2* is the default signal and it is selected immediately after master reset or power-up. txrdy* a/b 1,32 o transmit ready. (active low) this pin goes high when the transmit fifo of the st16c2552 is full. it can be used as a single or multi-transfer. rts* a/b 36,23 o request to send a/b (active low). to indicate that the transmitter has data ready to send. writing a 1 in the modem control register (mcr bit-1 ) will set this pin to a low state. after the reset this pin will be set to high. note that this pin does not have any effect on the transmit or receive operation. dtr* a/b 37,27 o data terminal ready a/b (active low). to indicate that st16c2552 is ready to receive data. this pin can be controlled via the modem control register (mcr bit-0). writing a 1 at the mcr bit-0 will set the dtr* output to low. this pin will be set to high state after writing a 0 to that register or after the reset . note that this pin does not have any effect on the transmit or receive operation. reset 21 i master reset. (active high) a high on this pin will reset all the outputs and internal registers. the transmitter output and the receiver input will be disabled during reset time.
3-139 st16c2552 st16c2552 symbol pin signal type pin description symbol description cts* a/b 40,28 i clear to send a/b (active low). the cts* signal is a modem control function input whose conditions can be tested by reading the msr bit-4. cts* has no effect on the transmit or receive operation. dsr* a/b 41,29 i data set ready a/b (active low). a low on this pin indicates the modem is ready to exchange data with uart. this pin does not have any effect on the transmit or receive opera- tion. cd* a/b 42,30 i carrier detect a/b (active low). a low on this pin indicates the carrier has been detected by the modem. ri* a/b 43,31 i ring detect indicator a/b (active low). a low on this pin indicates the modem has received a ringing signal from telephone line. vcc 33,44 i power supply input. gnd 12,22 o signal and power ground. programming table a2 a1 a0 read mode write mode 0 0 0 receive holding register transmit holding register 0 0 1 interrupt enable register 0 1 0 interrupt status register fifo control register 0 1 1 line control register 1 0 0 modem control register 1 0 1 line status register 1 1 0 modem status register 1 1 1 scratchpad register scratchpad register 0 0 0 lsb of divisor latch 0 0 1 msb of divisor latch 0 1 0 alternate function register alternate function register
3-140 st16c2552 st16c2552 st16c2552 accessible registers a/b a2 a1 a0 register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 rhr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 thr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier 0 0 0 0 modem receive transmit receive status line holding holding interrupt status register register interrupt 0 1 0 fcr rcvr rcvr 0 0 dma xmit rcvr fifo trigger trigger mode fifo fifo enable msb) (lsb) select reset reset 0 1 0 isr 0/ 0/ 0 0 int int int int fifos fifos priority priority priority status enabled enabled bit-2 bit-1 bit-0 0 1 1 lcr divisor set set even parity stop word word latch break parity parity enable bits length length enable bit-1 bit-0 1 0 0 mcr 0 0 0 loop op2* op1* rts* dtr* back 1 0 1 lsr 0/ trans. trans. break framing parity overrun receive fifo empty holding interrupt error error error data error empty ready 1 1 0 msr cd ri dsr cts delta delta delta delta cd* ri* dsr* cts* 1 1 1 spr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 dll bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 dlm bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 010afr00000mf*mf*sp sel-1 sel-0 write these registers are accessible only when lcr bit-7 is set to 1.
3-141 st16c2552 st16c2552 fifo polled mode operation when fcr bit-0=1; resetting ier bit 3-0 to zero puts the st16c2552 in the fifo polled mode of operation. since the receiver and transmitter are controlled separately either one or both can be in the polled mode operation by utilizing the line status register. a) lsr bit-0 will be set as long as there is one byte in the receive fifo. b) lsr bit4-1 will specify which error(s) has oc- curred. c) lsr bit-5 will indicate when the transmit fifo is empty. d) lsr bit-6 will indicate when both transmit fifo and transmit shift register are empty. e) lsr bit-7 will indicate when there are any errors in the receive fifo. programmable baud rate generator each uart section of the st16c2552 contains a programmable baud rate generator that is capable of taking any clock input from dc-24 mhz and dividing it by any divisor from 1 to 2 16 -1. the output frequency of the baudout* is equal to 16x of transmission baud rate (baudout*=16 x baud rate). customize baud rates can be achieved by selecting proper divisor values for msb and lsb of baud rate generator. interrupt enable register (ier) the interrupt enable register (ier) masks the incom- ing interrupts from receiver ready, transmitter empty, line status and modem status registers to the int output pin. ier bit-0: 0=disable the receiver ready interrupt. 1=enable the receiver ready interrupt. register functional descriptions transmit and receive holding register the serial transmitter section consists of a transmit hold register (thr) and transmit shift register (tsr). the status of the transmit hold register is provided in the line status register (lsr). writing to this register (thr) will transfer the contents of data bus (d7-d0) to the transmit holding register when- ever the transmitter holding register or transmitter shift register is empty. the transmit holding register empty flag will be set to 1 when the transmitter is empty or data is transferred to the transmit shift register. note that a write operation should be per- formed when the transmit holding register empty flag is set. on the falling edge of the start bit, the receiver internal counter will start to count 7 1/2 clocks (16x clock) which is the center of the start bit. the start bit is valid if the rx is still low at the mid-bit sample of the start bit. verifying the start bit prevents the receiver from assembling a false data character due to a low going noise spike on the rx input. receiver status codes will be posted in the line status register. fifo interrupt mode operation when the receive fifo (fcr bit-0=1) and receive interrupts (ier bit-0=1) are enabled, receiver inter- rupt will occur as follows: a) the receive data available interrupts will be issued to the cpu when the fifo has reached its pro- grammed trigger level; it will be cleared as soon as the fifo drops below its programmed trigger level. b) the isr receive data available indication also occurs when the fifo trigger level is reached, and like the interrupt it is cleared when the fifo drops below the trigger level. c) the data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receiver fifo. it is reset when the fifo is empty.
3-142 st16c2552 st16c2552 *receive time-out: this mode is enabled when startech uart is operating in fifo mode. receive time out will not occur if the receive fifo is empty. the time out counter will be reset at the center of each stop bit received or each time receive holding register is read. the actual time out value is t ( t ime out length in bits)= 4 x p ( p rogrammed word length) + 12. to convert time out value to a character value, user has to divide this number to its complete word length + parity ( if used) + number of stop bits and start bit. example -a: if user programs the word length = 7, and no parity and one stop bit, time out will be: t = 4 x 7( programmed word length) +12 = 40 bits character time = 40 / 9 [ (programmed word length = 7) + (stop bit = 1) + (start bit = 1)] = 4.4 characters. example -b: if user programs the word length = 7, with parity and one stop bit, the time out will be: t = 4 x 7(programmed word length) + 12 = 40 bits character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 characters. isr bit-0: 0=an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. 1=no interrupt pending. isr bit 1-3: logical combination of these bits, provides the high- est priority interrupt pending. isr bit 4-7: these bits are not used and are set to zero if the fifos are not enabled. bit 6-7: are set to 1 when the fifos are enabled. fifo control register (fcr) this register is used to enable the fifos, clear the fifos, set the receiver fifo trigger level, and select the type of dma signaling. fcr bit-0: 0=disable the transmit and receive fifo. 1=enable the transmit and receive fifo. ier bit-1: 0=disable the transmitter empty interrupt. 1=enable the transmitter empty interrupt. ier bit-2: 0=disable the receiver line status interrupt. 1=enable the receiver line status interrupt. ier bit-3: 0=disable the modem status register interrupt. 1=enable the modem status register interrupt. ier bit 4-7: all these bits are set to logic zero. interrupt status register (isr) the st16c2552 provides four level prioritized inter- rupt conditions to minimize software overhead during data character transfers. the interrupt status regis- ter (isr) provides the source of the interrupt in priori- tized matter. during the read cycle the st16c2552 provides the highest interrupt level to be serviced by cpu. no other interrupts are acknowledged until the particular interrupt is serviced. the following are the prioritized interrupt levels: priority level p d3 d2 d1 d0 source of the interrupt 10110 lsr (receiver line sta- tus register) 20100 rxrdy (received data ready) 2* 1 1 0 0 rxrdy (receive data time out) 30010 txrdy( transmitter holding register empty) 40000 msr (modem status register)
3-143 st16c2552 st16c2552 fcr bit-1: 0=no change. 1=clears the contents of the receive fifo and resets its counter logic to 0 (the receive shift register is not cleared or altered). this bit will return to zero after clearing the fifos. fcr bit-2: 0=no change. 1=clears the contents of the transmit fifo and resets its counter logic to 0 (the transmit shift register is not cleared or altered). this bit will return to zero after clearing the fifos. fcr bit-3: 0=no change. 1=changes rxrdy and txrdy pins from mode 0 to mode 1. transmit operation in mode 0: when st16c2552 is in st16c450 mode ( fcr bit- 0=0 ) or in the fifo mode ( fcr bit-0=1, fcr bit-3=0 ) when there are no characters in the transmit fifo or transmit holding register, the txrdy* pin will go low. once active the txrdy* pin will go high (inactive) after the first character is loaded into the transmit holding register. receive operation in mode 0: when st16c2552 is in st16c450 mode ( fcr bit- 0=0 ) or in the fifo mode ( fcr bit-0=1, fcr bit-3=0 ) and there is at least 1 character in the receive fifo, the rxrdy* pin will go low. once active the rxrdy* pin will go high (inactive) when there are no more characters in the receiver. transmit operation in mode 1: when st16c2552 is in st16c550 mode ( fcr bit- 0=1, fcr bit-3=1 ) the txrdy* pin will become high (inactive) when the transmit fifo is completely full. it will be low if one or more fifo locations are empty. receive operation in mode 1: when st16c2552 is in st16c550 mode ( fcr bit- 0=1, fcr bit-3=1 ) and the trigger level or the timeout has been reached, the rxrdy* pin will go low. once it is activated it will go high (inactive) when there are no more characters in the fifo. fcr bit 4-5: not used. fcr bit 6-7: these bits are used to set the trigger level for the receiver fifo interrupt. bit-7 bit-6 fifo trigger level 00 01 01 04 10 08 11 14 alternate function register (afr) this is a read/write register used to select specific modes of mf* operation and to allow both uart registers sets to be written concurrently. afr bit-0: when this bit is set, cpu can write concurrently to the same register in both uarts. this function is intended to reduce the dual uart initialization time. it can be used by cpu when both channels are initialized to the same state. cpu can set or clear this bit by accessing either register set. when this bit is set the channel select pin still selects the channel to be accessed during read operation. setting or clearing this bit has no effect on read operations. the user should ensure that lcr bit-7 of both chan- nels are in the same state before executing a concur- rent write to the registers at address 0,1, or 2. afr bit 1-2: combinations of these bits selects one of the mf* functions.
3-144 st16c2552 st16c2552 bit-2 bit-1 mf* function 0 0 op2* 0 1 baudout* 1 0 rxrdy* 1 1 reserved afr bit 3-7: not used. all these bits are set to logic zero. line control register (lcr) the line control register is used to specify the asynchronous data communication format. the num- ber of the word length, stop bits, and parity can be selected by writing appropriate bits in this register. lcr bit1-0: these two bits specify the word length to be transmit- ted or received. bit-1 bit-0 word length 00 5 01 6 10 7 11 8 lcr bit-2: the number of stop bits can be specified by this bit. bit-2 word length stop bit(s) 0 5,6,7,8 1 1 5 1-1/2 1 6,7,8 2 lcr bit-3: parity or no parity can be selected via this bit. 0=no parity 1=a parity bit is generated during the transmission, receiver also checks for received parity. lcr bit-4: if the parity bit is enabled, lcr bit-4 selects the even or odd parity format. 0=odd parity is generated by forcing an odd number of 1s in the transmitted data, receiver also checks for same format. 1= even parity bit is generated by forcing an even number of 1s in the transmitted data, receiver also checks for same format. lcr bit-5: if the parity bit is enabled, lcr bit-5 selects the forced parity format. lcr bit-5=1 and lcr bit-4=0, parity bit is forced to 1 in the transmitted and received data. lcr bit-5=1 and lcr bit-4=1, parity bit is forced to 0 in the transmitted and received data. lcr bit-6: break control bit. it causes a break condition to be transmitted (the tx is forced to low state). 0=normal operating condition. 1=forces the transmitter output (tx) to go low to alert the communication terminal. lcr bit-7: the internal baud rate counter latch enable (dlab). 0=normal operation. 1=select divisor latch register and alternate func- tion register. modem control register (mcr) this register controls the interface with the modem or a peripheral device (rs232). mcr bit-0: 0=force dtr* output to high. 1=force dtr* output to low. mcr bit-1: 0=force rts* output to high. 1=force rts* output to low.
3-145 st16c2552 st16c2552 mcr bit-2: not used except in local loop-back mode. mcr bit-3: 0=force op2* output to high. 1=force op2* output to low. mcr bit-4: 0=normal operating mode. 1=enable local loop-back mode (diagnostics). the transmitter output (tx) is set high (mark condition), the receiver input (rx) , cts*, dsr*, cd*, and ri* are disabled. internally the transmitter output is con- nected to the receiver input and dtr*, rts*, op1* and op2* are connected to modem control inputs. in this mode , the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational, but the interrupts sources are now the lower four bits of the modem control register instead of the four modem control inputs. the inter- rupts are still controlled by the ier . mcr bit 5-7: not used. are set to zero permanently. line status register (lsr) this register provides the status of data transfer to cpu. lsr bit-0: 0=no data in receive holding register or fifo. 1=data has been received and saved in the receive holding register or fifo. lsr bit-1: 0=no overrun error (normal). 1=overrun error, next character arrived before receive holding register was emptied or if fifos are enabled, an overrun error will occur only after the fifo is full and the next character has been completely received in the shift register. note that character in the shift register is overwritten, but it is not transferred to the fifo. lsr bit-2: 0=no parity error (normal). 1=parity error, received data does not have correct parity information. in the fifo mode this error is associated with the character at the top of the fifo. lsr bit-3: 0=no framing error (normal). 1=framing error received, received data did not have a valid stop bit. in the fifo mode this error is associated with the character at the top of the fifo. lsr bit-4: 0=no break condition (normal). 1=receiver received a break signal (rx was low for one character time frame). in fifo mode, only one zero character is loaded into the fifo. lsr bit-5: 0=transmit holding register is full. st16c2552 will not accept any data for transmission. 1=transmit holding register (or fifo ) is empty. cpu can load the next character. lsr bit-6: 0=transmitter holding and shift registers are full. 1=transmitter holding and shift registers are empty. in fifo mode this bit is set to one whenever the trans- mitter fifo and transmit shift register are empty. lsr bit-7: 0=normal. 1=at least one parity error, framing error or break indication in the fifo. this bit is cleared when lsr is read. modem status register (msr) this register provides the current state of the control lines from the modem or peripheral to the cpu. four bits of this register are used to indicate the changed information. these bits are set to 1 whenever a control input from the modem changes state. they are set to 0 whenever the cpu reads this register.
3-146 st16c2552 st16c2552 msr bit-0: indicates that the cts* input to the st16c2552 has changed state since the last time it was read. msr bit-1: indicates that the dsr* input to the st16c2552 has changed state since the last time it was read. msr bit-2: indicates that the ri* input to the st16c2552 has changed from a low to a high state. msr bit-3: indicates that the cd* input to the st16c2552 has changed state since the last time it was read. msr bit-4: this bit is equivalent to rts in the mcr during local loop-back mode. it is the compliment of the cts* input. msr bit-5: this bit is equivalent to dtr in the mcr during local loop-back mode. it is the compliment of the dsr* input. msr bit-6: this bit is equivalent to op1 in the mcr during local loop-back mode. it is the compliment of the ri* input. msr bit-7: this bit is equivalent to op2 in the mcr during local loop-back mode. it is the compliment to the cd* input. note: whenever msr bit3-0: is set to logic 1, a modem status interrupt is generated. scratchpad register (sr) st16c2552 provides a temporary data register to store 8 bits of information for variable use. baud rate generator programming table (1.8432 mhz clock): baud rate 16 x clock % error divisor 50 2304 75 1536 150 768 300 384 600 192 1200 96 2400 48 4800 24 7200 16 9600 12 19.2k 6 38.4k 3 56k 2 2.77 115.2k 1 st16c2552 external reset condition registers reset state ier ier bits 0-7=0 isr isr bit-0=1, isr bits 1-7=0 lcr lcr bits 0-7=0 mcr mcr bits 0-7=0 lsr lsr bits 0-4=0, lsr bits 5-6=1 lsr, bit 7=0 msr msr bits 0-3=0, msr bits 4-7=input signals fcr fcr bits 0-7=0 mfr afr bits 0-7=0 signals reset state tx high op2* high rts* high dtr* high int low txrdy* low
3-147 st16c2552 st16c2552 absolute maximum ratings supply voltage 7 volts voltage at any pin gnd-0.3 v to vcc+0.3 v operating temperature 0 c to +70 c storage temperature -40 c to +150 c package dissipation 500 mw symbol parameter limits units conditions min typ max dc electrical characteristics t a =0 - 70 c, vcc=5.0 v 10% unless otherwise specified. v ilck clock input low level -0.5 0.6 v v ihck clock input high level 3.0 vcc v v il input low level -0.5 0.8 v v ih input high level 2.2 vcc v v ol output low level on all outputs 0.4 v i ol = 6 ma v oh output high level 2.4 v i oh = -6 ma i cc avg. power supply current 2 2.5 ma i il input leakage 10 m a i cl clock leakage 10 m a this product can operate in 3.0 volts environment. please consult with factory for additional information.
3-148 st16c2552 st16c2552 symbol parameter limits units conditions min typ max ac electrical characteristics t a =0 - 70 c, vcc=5.0 v 10% unless otherwise specified. t 1 clock high pulse duration 20 ns t 2 clock low pulse duration 20 ns t 3 clock rise/fall time 10 ns t 8 chip select setup time 0 ns t 9 chip select hold time 0 ns t 12 data set up time 15 ns t 13 data hold time 15 ns t 14 iow* delay from chip select 10 ns t 15 iow* strobe width 50 ns t 16 chip select hold time from iow* 0 ns t 17 write cycle delay 55 ns tw write cycle=t 15 +t 17 105 ns t 19 data hold time 15 ns t 21 ior* delay from chip select 10 ns t 23 ior* strobe width 65 ns t 24 chip select hold time from ior* 0 ns t 25 read cycle delay 55 ns tr read cycle=t 23 +t 25 115 ns t 26 delay from ior* to data 35 ns 100 pf load t 28 delay from iow* to output 50 ns 100 pf load t 29 delay to set interrupt from modem 70 ns 100 pf load input t 30 delay to reset interrupt from ior* 70 ns 100 pf load t 31 delay from stop to set interrupt 1 rclk ns 100 pf load t 32 delay from ior* to reset interrupt 200 ns 100 pf load t 33 delay from initial int reset to transmit 8 24 * start t 34 delay from stop to interrupt 100 ns t 35 delay from iow* to reset interrupt 175 ns t 36 delay from initial write to interrupt 16 24 * t 44 delay from stop to set rxrdy 1 rclk t 45 delay from ior* to reset rxrdy 100 ns t 46 delay from iow* to set txrdy 195 ns t 47 delay from start to reset txrdy 8 * t r reset pulse width 10 ns n baud rate devisor 1 2 16 -1 note 1: * = baudout* cycle
3-149 st16c2552 st16c2552 clock timing t1 t2 t3 t3 external clock clock period clock period 161450-ck-1 a0-a2 cs* ior* d0-d7 t8 t9 t23 t21 t24 t25 t26 t19 general read timing 162552-rd-1 chsel
3-150 st16c2552 st16c2552 a0-a2 general write timing cs* iow* d0-d7 t8 t9 t15 t14 t16 t17 t12 t13 162552-wd-1 chsel
3-151 st16c2552 st16c2552 iow* rts* dtr* cd cts dsr intx ior* ri modem timing t28 t29 t29 t30 t29 162450-md-1
3-152 st16c2552 st16c2552 stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit receive timing rx next data start bit intx ior* t31 t32 16 baud rate clock 162450-rx-1
3-153 st16c2552 st16c2552 stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit rxrdy timing for mode "0" rx (first byte) rxrdy* ior* t44 t45 16552-rx-2
3-154 st16c2552 st16c2552 stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit rxrdy timing for mode "1" rx rxrdy* ior* t44 t45 first byte that reaches the trigger level 16552-rx-3
3-155 st16c2552 st16c2552 stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit transmit timing tx next data start bit intx iow* t34 t35 t33 16 baud rate clock 162450-tx-1
3-156 st16c2552 st16c2552 stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit txrdy timing for mode "0" tx iow* d0-d7 txrdy* byte #1 t46 t47 162550-tx-2
3-157 st16c2552 st16c2552 stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit txrdy timing for mode "0" tx iow* d0-d7 txrdy* byte #1 t46 t47 162550-tx-2
3-158 st16c2552 st16c2552
package dimensions 44 lead plastic leaded chip carrier (plcc) rev. 1.00 1 d d 1 a a 1 d d 1 d 3 a 0.165 0.180 4.19 4.57 a 1 0.090 0.120 2.29 3.05 a 2 0.020 . 0.51 b 0.013 0.021 0.33 0.53 b 1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.685 0.695 17.40 17.65 d 1 0.650 0.656 16.51 16.66 d 2 0.590 0.630 14.99 16.00 d 3 0.500 typ. 12.70 typ. e 0.050 bsc 1.27 bsc h1 0.042 0.056 1.07 1.42 h2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 symbol min max min max inches millimeters b a 2 b 1 e seating plane d 2 244 note: the control dimension is the inch column d 3 45 x h2 45 x h1 c r
notes
notes
notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright 1993 exar corporation reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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